Conventionally, in order to supply data and address signals from a CPU to a peripheral circuit, there are provided an external address latch and a multiplexed address/data bus connected with the CPU. The multiplexed address/data bus is used for transferring both data signals and lower address signals in a time-sharing manner with the address latch temporarily storing the lower address signals. Thus, a peripheral circuit receives upper address signals directly supplied from the CPU and lower address signals from the address latch.
During program development, a detachable external ROM is used as a program memory for a CPU when a program is likely to contain many bugs. After the program is finalized, the external ROM is connected in the conventional circuit device as described above.
A digital electronic circuit device first proposed by the inventor of the present invention (who was under an obligation to assign the subject matter of FIGS. 3 and 4 to the assignee of the present invention) is constructed as shown in FIG. 3. A multiplexed address/data bus 8 is connected between a peripheral element 3 and multiplexed address/data terminals A0.about.A7, D0.about.D7 of a CPU 1. An address bus 7 is connected between an address terminal A13 of the CPU 1, exclusively used for an address signal, and a chip-select terminal CS the peripheral element 3. An address latch 4 together with a detachable external ROM 2 (Electrically Programmable ROM) are connected to the multiplexed address/data bus 8, and an output-enable terminal OE of the address latch 4 is connected to the address terminal A13 of the CPU 1 through the address bus 7. After the address latch 4 has held lower address signals, given from the CPU 1 through the multiplexed address/data bus 8, for a required period, the latch 4 outputs the lower address signals to the external ROM 2 through an address bus 9. Latch 4 also outputs a part of the lower address signals to address terminals A0, A1 of the peripheral element 3, through an address bus 11. The external ROM 2 outputs its stored data signals to the multiplexed address/data bus 8, through a data bus 10 when the ROM 2 receives the lower address signals, outputted from the address latch 4 through the address bus 9, and upper address signals, outputted from exclusive address terminals A8.about.A12 of the CPU 1 through an address bus 6.
When a program for the CPU 1 is debugged, the external ROM 2 may be replaced by a masked ROM internal to a CPU, in which the revised program is written in a process of producing the CPU. The external ROM 2 can be removed without affecting other circuits. However, it is impossible to remove address latch 4 because the address bus 11, connected with the address terminals A0, A1 of the peripheral element 3, is connected with the multi-plexed address/data terminals A0.about.A7, D0.about.D7, through the address latch 4 and the multiplexed address/data bus 8.
FIG. 4 shows a digital electronic circuit device wherein the CPU 1 shown in FIG. 3 is replaced with a CPU 21 equipped inside with a masked ROM 22 and the external ROM 2 has been removed. The address latch 4 remains only for holding address signals to be supplied to the peripheral element 3. Consequently, it is difficult to decrease the number of circuit elements and the number of assembling processes, so that the digital electronic circuit device may not be produced at a lower cost.